Job responsibilities:
• Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
• Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimation
• Verify Logic at ISP level and Digital System level
• Optimize Design for less gate count and low power consumption
• Drive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design Team
Qualifications:
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7+ years experience with Digital Design and verification
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Experience / knowledge in Camera Image Signal Processing
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Experience / knowledge in C/C++ programming
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Experience as a Technical Leader to develop Digital System on silicon
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Strong debugging and problem-solving skills
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Good communication and interpersonal skills
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Result oriented and embrace change behaviors
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Experience / knowledge in High Level Synthesis is a plus
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Experience / knowledge in CMOS Image Sensor is a plus
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Language skill: Japanese Business and English Business
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Project management / people management experience / skill is a plus
