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We are seeking a highly skilled Senior Analog Layout Engineer to lead the physical layout of complex analog, mixed‑signal, and high‑performance IC designs. This role requires deep expertise in custom layout techniques, advanced process nodes, physical verification, and close collaboration with circuit designers to deliver silicon‑proven designs that meet stringent performance, reliability, and manufacturing requirements.

Primary Responsibilities:

Own and execute the full layout lifecycle for analog and mixed‑signal IP blocks such as ADCs, DACs, PLLs, LDOs, bandgaps, amplifiers, and pixels.
Collaborate closely with circuit design engineers to understand specifications, constraints, and performance trade-offs.
Develop floorplans, layout strategies, and routing plans that optimize matching, noise performance, EM/IR robustness
Perform custom layout of critical analog circuits using industry‑standard EDA tools (e.g., Cadence Virtuoso).
Ensure compliance with design rules (DRC), electrical rules (ERC), layout-vs-schematic checks (LVS), and parasitic extraction (PEX).
Drive layout quality through guard‑ringing, shielding, isolation techniques, symmetry enforcement, and dummy placements.
Work with foundry PDKs to interpret process rules, device models, and reliability requirements (ESD, EM, latch‑up).
Generate and maintain layout documentation, checklists, and layout guidelines for internal use.
Prepare designs for tapeout, including final checks, documentation, and coordination with the fabrication team.
Develop and maintain scripts to automate repetitive tasks, improving efficiency and consistency in the design process.
Participate in technical reviews with design team and customer.
Able to work independently and collaborate with local technical lead.

Position Requirements:

Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or related field.
4-7+ years of experience in analog or mixed‑signal IC layout.
Expert proficiency with Cadence Virtuoso or equivalent layout platforms.

Deep understanding of:

Analog layout matching and common centroid techniques
Low‑noise, low‑offset layout methodologies
Parasitic‑aware design and optimization
Strong understanding of DRC, LVS, PEX flows and physical verification tools (Calibre, Assura, PVS).
Ability to work in a fast‑paced, collaborative environment with designers, CAD engineers, and verification teams.
Excellent communication and documentation skills.

About Us: Forza Silicon is a Business Unit in the Materials Analysis Division of AMETEK, Inc. Founded in 2001, Forza Silicon has established itself as an innovator and industry leader in the field of mixed-signal IC and CMOS imaging designs that have set the standard of the possible. Primarily through long standing customer relationships and partner referrals, Forza has grown to where today the company employs one of the industry’s largest and most experienced independent CMOS imaging engineering teams. To learn more about Forza Silicon, please go to www.forzasilicon.com

Compensation

Currency: JPY

Salary Minimum: Market

Salary Maximum: Market

Incentive: Market

Disclaimer: Where a specific pay range is noted, it is a good faith estimate at the time of this posting. The actual salary offered will be based on experience, skills, qualifications, market / business considerations, and geographic location.

AMETEK, Inc. is a leading global provider of industrial technology solutions serving a diverse set of attractive niche markets with annual sales over $7.5 billion.

AMETEK is committed to making a safer, sustainable, and more productive world a reality. We use differentiated technology solutions to solve our customers’ most complex challenges. We employ 22,000 colleagues, in 35 countries, that are grounded by our core values: Ethics and Integrity, Respect for the Individual, Inclusion, Teamwork, and Social Responsibility. AMETEK is a component of the S&P 500. Visit https://www.ametek.com/careers for more information.

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